Unlike a capacitor memory device in which memory characteristics are proportional to the size of a cell area, the resistive type memory devices require noticeably less area budget, and therefore are capable of achieving significantly higher level of integration.
However, while the write speed of these highly integratable memory cells are theoretically identical, the reality is that some memory cells are programmed or erased faster than others, resulting in a distribution of threshold voltage for each state. Conventional solution is to group the memory bits in small numbers and provide fixed program pulses separately with write-verifications in between. However, the fixed program pulse in such a scheme is required to match the memory cell of a fastest reaction time, while the cumulative program pulse duration need to match the memory cell of a slowest reaction time, thereby inevitably sacrificing overall programming throughput.